Microprocessor
Microprocessor
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A microprocessor -- also known as a CPU or central processing unit -- is a complete computation engine that is fabricated on a single chip.
The first microprocessor was the Intel 4004, introduced in 1971. The 4004 was not very powerful -- all it could do was add and subtract, and it could only do that 4 bits at a time. But it was amazing that everything was on one chip.
Prior to the 4004, engineers built computers either from collections of chips or from discrete components (transistors wired one at a time). The 4004 powered one of the first portable electronic calculators.
A microprocessor is an integrated circuit (IC) that contains the core functions of a computer's Central Processing Unit (CPU) on a single silicon chip. It acts as the central brain of a computer system, executing instructions, processing arithmetic and logic operations, and managing data flow between memory and peripheral devices.
Core Components
Arithmetic Logic Unit (ALU): Performs all mathematical calculations (addition, subtraction, multiplication) and logical comparisons (AND, OR, NOT).
Control Unit (CU): Directs the operations of the processor by decoding program instructions and generating timing/control signals for data routing.
Register Array: Small, ultra-fast internal storage units used to hold immediate operands, memory addresses, flags, and instruction pointers (such as the Program Counter and Accumulator).
Internal Bus & Cache: High-speed internal data pathways and local SRAM memory caches (L1, L2, L3) that reduce latency when fetching data from main system RAM.
How a Microprocessor Works (The Machine Cycle)
The microprocessor continuously operates through the Fetch-Decode-Execute cycle:
Fetch: Retrieves the next instruction code from memory using the address held in the Program Counter.
Decode: The Control Unit interprets the instruction opcode to determine the required actions and operands.
Execute: The ALU or execution units perform the specified operation and write back the output to registers or system memory.
Moore's Law
Moore's Law
Moore's law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years. Moore's law is an observation and projection of a historical trend.
Rather than a law of physics, it is an empirical relationship linked to gains from experience in production.
The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and Intel (and former CEO of the latter), who in 1965 posited a doubling every year in the number of components per integrated circuit, and projected this rate of growth would continue for at least another decade.
Die (integrated circuit)
Die (integrated circuit)
A die, in the context of integrated circuits, is a small block of semiconducting material on which a given functional circuit is fabricated.
Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor (such as GaAs) through processes such as photolithography.
The wafer is cut (diced) into many pieces, each containing one copy of the circuit. Each of these pieces is called a die.
Then the dies are sorted to filter out the faulty dies. Functional dies are then packaged and the completed integrated circuit is ready to be shipped.
Die Shrink
Die Shrink
The term die shrink (sometimes optical shrink or process shrink) refers to the scaling of metal-oxide-semiconductor (MOS) devices.
The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, usually involving an advance of lithographic nodes.
This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs, while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in less cost per product sold.
Clock Speed
Clock Speed
In a computer, clock speed refers to the number of pulses per second generated by an oscillator that sets the tempo for the processor.
Clock speed is usually measured in MHz (megahertz, or millions of pulses per second) or GHz (gigahertz, or billions of pulses per second). Today's personal computers run at a clock speed in the hundreds of megahertz and some exceed one gigahertz.
The clock speed is determined by a quartz-crystal circuit, similar to those used in radio communications equipment. Computer clock speed has been roughly doubling every year.
The Intel 8088, common in computers around the year 1980, ran at 4.77 MHz. The 1 GHz mark was passed in the year 2000. Clock speed is one measure of computer "power," but it is not always directly proportional to the performance level.
If you double the speed of the clock, leaving all other hardware unchanged, you will not necessarily double the processing speed. The type of microprocessor, the bus architecture, and the nature of the instruction set all make a difference. In some applications, the amount of random access memory (RAM) is important, too.
System bus
System bus
A system bus is a single computer bus that connects the major components of a computer system, combining the functions of a data bus to carry information, an address bus to determine where it should be sent or read from, and a control bus to determine its operation.
The system level bus (as distinct from a CPU's internal datapath busses) connects the CPU to memory and I/O devices.
Typically a system level bus is designed for use as a backplane.
Processor Core
Processor Core
A core, or CPU core, is the "brain" of a CPU. It receives instructions, and performs calculations, or operations, to satisfy those instructions. A CPU can have multiple cores.
A processor with two cores is called a dual-core processor; with four cores, a quad-core; six cores, hexa-core; eight cores, octa-core. The majority of consumer CPUs feature between two and twelve cores.
Workstation and server CPUs may feature as many as 48. Each core of a CPU can perform operations separately from the others.
Or, multiple cores may work together to perform parallel operations on a shared set of data in the CPU's memory cache.
Cache
Cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.
A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations.
Most CPUs have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with separate instruction-specific and data-specific caches at level 1.
Von Neumann vs Harvard
Von Neumann vs Harvard
Memory Organization
Von Neumann: Stores both machine instructions (code) and user data within the same shared physical memory space.
Harvard: Maintains physically separate memory units for instructions and data.
Bus System
Von Neumann: Uses a single, shared bus set (data, address, and control) for both fetching instructions and moving data.
Harvard: Uses separate sets of buses—a dedicated instruction bus and a dedicated data bus.
Execution Speed & Pipelining
Von Neumann: Must execute memory operations sequentially; the CPU cannot fetch an instruction and read/write data in the exact same clock cycle.
Harvard: Supports concurrent memory access; the processor can fetch the next instruction while simultaneously reading or writing operand data.
Hardware Complexity & Cost
Von Neumann: Simpler physical implementation requiring fewer pins, physical traces, and control logic on the chip.
Harvard: More complex and expensive to fabricate due to duplicated buses, additional memory controllers, and higher pin counts.
Memory Utilization & Flexibility
Von Neumann: Highly efficient memory usage; available RAM dynamically reallocates depending on whether an application requires more code space or more data storage.
Harvard: Rigid memory allocation; unused instruction memory cannot be repurposed for data storage, potentially leading to wasted space.
System Bottleneck
Von Neumann: Prone to the Von Neumann Bottleneck, where CPU throughput is throttled by bus contention and memory bandwidth limits.
Harvard: Eliminates shared-bus contention, providing significantly higher memory throughput.
Primary Applications
Von Neumann: General-purpose computers, desktops, laptops, and server architectures.
Harvard: Microcontrollers (e.g., PIC, AVR), Digital Signal Processors (DSPs), and specialized embedded systems. Modern desktop CPUs (x86/ARM) typically operate as a Modified Harvard hybrid, utilizing separate L1 instruction and data caches internally while sharing a unified external main memory.
CISC vs RISC
CISC vs RISC
CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) are two fundamental CPU design philosophies that take opposing approaches to instruction sets, hardware complexity, and compiler responsibility.
CISC (Complex Instruction Set Computer)
Design Philosophy: Minimize instructions per program by executing high-level, multi-step operations directly in hardware.
Instruction Format: Variable length, requiring complex decoding logic.
Execution Time: Variable, often requiring multiple clock cycles per instruction.
Memory Model: Direct memory-to-memory operations (instructions can read from, compute on, and write to RAM directly).
Hardware vs. Software: Emphasizes complex hardware (microcode engines) to keep compiler design simpler and reduce binary sizes.
Registers: Fewer general-purpose registers.
Common Examples: x86/x86-64 (Intel, AMD).
RISC (Reduced Instruction Set Computer)
Design Philosophy: Maximize execution speed by executing small, simple, and uniform instructions.
Instruction Format: Fixed length (usually 32-bit), making instruction fetch and decode straightforward.
Execution Time: Uniform, aiming for 1 clock cycle per instruction.
Memory Model: Load/Store architecture (arithmetic/logic operations only occur between registers; dedicated LOAD and STORE instructions handle RAM access).
Hardware vs. Software: Emphasizes simple hardware and efficient pipelining, shifting optimization responsibility to the compiler.
Registers: Large bank of general-purpose registers.
Common Examples: ARM (Apple Silicon, smartphones), RISC-V, MIPS.
Core Architectural Differences
Instruction Complexity: CISC uses rich, multi-operation instructions (e.g., a single MULT instruction can fetch two memory addresses, multiply them, and write back the result). RISC breaks this into separate LOAD, MUL, and STORE instructions.
Pipelining Efficiency: RISC architectures pipeline easily due to fixed instruction sizes and predictable execution times. CISC pipelining is harder due to variable instruction lengths and multi-cycle execution.
Code Density vs. Memory Access: CISC generates smaller binary footprints (fewer assembly instructions), which was historically critical when RAM was expensive. RISC binaries are slightly larger, but execute faster with less power consumption.
Modern Convergence
Modern high-performance processors blend both philosophies. Modern x86 (CISC) processors use a hardware decoder at the front end that breaks down complex CISC instructions into simple, RISC-like internal operations (called micro-ops), which are then executed on an out-of-order, superscalar RISC-style execution core.
CPU Socket
CPU Socket
In computer hardware, a CPU socket or CPU slot contains one or more mechanical components providing mechanical and electrical connections between a microprocessor and a printed circuit board (PCB). This allows for placing and replacing the central processing unit (CPU) without soldering.
Common sockets include Pin Grid Array (PGA) or Land Grid Array (LGA). These designs apply a compression force once either a handle (PGA type) or a surface plate (LGA type) is put into place.
This provides superior mechanical retention while avoiding the risk of bending pins when inserting the chip into the socket.
Ball grid array
Ball grid array
A ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits.
BGA packages are used to permanently mount devices such as microprocessors.
A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter.
The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds
Memory Hirerarchy
Memory Hirerarchy
Memory Hierarchy organizes computer storage into distinct levels based on access time, cost per bit, and total capacity to balance fast CPU performance with cost-effective storage.
Levels of the Hierarchy (Top to Bottom)
CPU Registers: Located directly inside the CPU core. They hold active instructions and immediate calculation operands, offering single-cycle access speeds (under 1 ns) with minimal capacity (typically a few kilobytes).
Cache Memory (SRAM): High-speed static RAM organized in tiers (L1, L2, L3). It acts as a buffer between the fast processor and slower RAM by holding frequently accessed data, running with latency between 1 to 10 ns.
Main Memory (DRAM / RAM): The primary workspace where active operating system processes and running applications reside. It offers gigabytes of volatile storage with access times around 50 to 100 ns.
Secondary Storage (SSDs / HDDs): Non-volatile mass storage (NAND Flash, Solid State Drives, Hard Drives) holding the operating system, file system, and user data. Access latency is in microseconds (SSDs) or milliseconds (HDDs).
Tertiary / Offline Storage: High-capacity archival systems, such as magnetic tape and optical discs, utilized for cold backup data and disaster recovery.
Core Trade-Offs
Moving Up: Access speed increases, cost per bit increases, and capacity decreases.
Moving Down: Capacity increases, cost per bit decreases, and latency increases.
The entire system relies on the Principle of Locality (temporal and spatial locality): programs tend to reuse recent memory addresses and access adjacent data chunks, ensuring the vast majority of memory requests hit fast cache layers rather than waiting on slower lower levels.
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